1. Field of the Invention
The present invention relates to an algorithmic analog-to-digital converter (ADC), and more particularly, to an algorithmic ADC having a reduced chip size and improved power efficiency.
2. Discussion of Related Art
Mobile communication terminals convert a received analog signal into a digital signal that is insusceptible to noise, and this conversion process is performed by an ADC. In particular, mobile communication terminals require high portability and thus need a small and low-power ADC.
Among already-known various ADCs, an algorithmic ADC is widely used to optimize a chip size and power consumption.
FIG. 1 is a circuit diagram of a conventional algorithmic ADC, and FIG. 2 shows circuit diagrams of first and second flash ADCs shown in FIG. 1.
As illustrated in FIG. 1, a conventional algorithmic ADC 100 includes first and second flash ADCs 110a and 110b, a multiplying digital-to-analog converter (MDAC) 150, and a digital correction circuit 170.
Each of the first and second flash ADCs 110a and 110b receives an analog signal, converts it into a digital signal, and outputs the digital signal. As illustrated in FIG. 2, the first and second flash ADCs 110a and 110b each include a plurality of preprocessing amplifiers 111 and a plurality of latches 113.
The MDAC 150 includes first and second DACs 120a and 120b, a subtractor 130, and an operational amplifier 140. Residual voltage left after digitization by the first and second flash ADCs 110a and 110b is again converted into an analog signal and output.
The digital correction circuit 170 corrects errors of the digital signals output from the first and second flash ADCs 110a and 110b. When the first and second flash ADCs 110a and 110b have n-bit resolution in the conventional algorithmic ADC 100, 2n−1 number of the preprocessing amplifiers 111 are used in the first and second flash ADCs 110a and 110b. Here, when the first and second flash ADCs 110a and 110b have a resolution of 4 bits or more, chip size significantly increases due to the preprocessing amplifiers 111.
Even if the first and second flash ADCs 110a and 110b have, for example, 3-bit resolution, 7 of the preprocessing amplifiers 111 are used in each of the first and second flash ADCs 110a and 110b. In total, 14 of the preprocessing amplifiers 111 are used, and thus chip size increases.
In addition, in the conventional algorithmic ADC 100, the MDAC 150 performs digital-to-analog signal conversion in each conversion step according to a clock signal CK having a specific period. Thus, the period of the signal conversion operation is fixed, and more current than necessary is consumed in a step of outputting low bits.